Bitwise AND operation between NOT operated int64 vectors. Corresponding instruction is VPANDNQ. This intrinsic only applies to Intel® Many Integrated Core Architecture (Intel® MIC Architecture).
Syntax
Without Mask extern _m512i __cdecl _mm512_andnot_epi64(_m512i v2, _m512i v3); |
With Mask extern _m512i __cdecl _mm512_mask_andnot_epi64(_m512i v1_old, __mmask8 k1, _m512i v2, _m512i v3); |
Parameters
v2 | int64 vector used for bitwise operation |
v3 | int64 vector also used for bitwise operation |
v1_old | Source vector that retains old values of the destination vector; the resulting vector gets corresponding elements from v1_old for zero mask bits |
k1 | Writemask; only those elements of the source vectors with corresponding bit set to '1' in the k1 mask are computed and stored in the result; elements in the result vector corresponding to zero bit in k1 are copied from corresponding elements of vector v1_old |
Description
Performs a bitwise AND operation between int64 vectors v2 and v3, each of which were previously operated upon by the NOT bitwise operator.
The masked variant has one additional argument: k1. Only those elements in the source registers with the corresponding bit set in vector mask k1 are used for computing. The remaining elements of the resulting vector are filled with corresponding elements from v1_old.